1. Field of Invention
The present invention relates to an image pixel, a dark node for use in the image pixel, and a control method for controlling the image pixel; particularly, it relates to such image pixel which is not sensitive to power supply noise because the dark node therein is capable of retaining power supply information.
2. Description of Related Art
Please refer to FIG. 1, which shows a schematic diagram of a conventional image pixel. The conventional image pixel 10 comprises plural light nodes (LN) 101 and plural dark nodes (DN) 102 arranged in a form of, for example, a 30 μm×30 μm array, wherein the dark nodes 102 are arranged at one peripheral side in order to increase the fill factor of the array. A dark node 102 is shared by the light nodes 101 of the same column.
Typically, the conventional image pixel 10 operates by three phases, which are: a reset phase, a shutter phase and a readout phase. The reset phase resets the charges stored in the nodes. The shutter phase exposes the pixel. The readout phase takes two samples, Sample 1 and Sample 2. Sample 1 is for sampling the light signal, which can be represented as: (DN−LN)Sample1, that is, the data obtained by the dark node minus the data obtained by the light node; and Sample 2 is for sampling the reset signal, which can be represented as: (DN−LN)Sample2. The signal of the conventional image pixel 10 is obtained by subtracting the reset signal from the light signal, and can be represented as:
the signal of image pixel 10=(DN−LN)Sample1−(DN−LN)Sample2. The readout phase is performed sequentially for every light node, that is, after one light node and a corresponding dark node are read out [i.e., two samples (Sample 1 and Sample 2) are taken from them], a next light node and a dark node corresponding to this light next node are read out.
Please refer to FIGS. 2A and 2B. FIG. 2A shows a schematic diagram of a conventional light node during a reset phase. FIG. 2B shows a schematic diagram of a conventional dark node during the reset phase. During the reset phase, a capacitor C0 of the light node 101 and a capacitor C1 of the dark node 102 are reset (connected to the power supply by the switches LS2 and DS2, whereas the switches LS1, LS3, LS4, DS1, DS3 and DS4 are opened), so that the power supply information V1 is stored in the capacitor C1 (FIG. 2B), and the voltage V0 of the capacitor C0 (FIG. 2A) is the same as V1. That is, in the reset phase, the voltage V1 of the capacitor C1 is reset to be corresponding to the power supply and the voltage V0 of the capacitor C0 is reset to V1.
Please refer to FIGS. 3A and 3B. FIG. 3A shows a schematic diagram of a conventional light node during a shutter phase. FIG. 3B shows a schematic diagram of a conventional dark node during the shutter phase. During the shutter phase, the switches LS2 and DS2 are opened; the switch LS3 is closed, while the switch DS3 remains opened. The other switches remain opened. The capacitor C0 of the light node 101 performs integration in response to light, so as to produce an integration voltage Vint (as shown in FIG. 3A); in the meanwhile, the power supply information V1 stored in the capacitor C1 of the dark node 102 remains the same. The integration voltage Vint is not equal to the power supply information V1, and the difference is related to the exposure.
Please refer to FIGS. 4A and 4B. FIG. 4A shows a schematic diagram of a conventional light node during a first sample stage (Sample 1) of a readout phase. FIG. 4B shows a schematic diagram of a conventional dark node during the first sample stage of the readout phase. As described above, Sample 1 is for sampling the light signal, which can be represented as: (DN−LN)Sample1. According to FIGS. 3A-3B, the voltage of the capacitor C0 of the light node 101 is “Vint”, and the power supply information stored in the capacitor C1 of the dark node 102 is “V1”. Hence, during Sample 1, a differential signal between the power supply information Vint and V1 can be obtained by closing the switches LS4 and DS4, and an analog-to-digital converter (ADC, not shown) receives these two signals through source follower effects provided by transistors LM1 and DM1, where the input of ADC is equal to (V1-Vint) multiplied by the gain of source followers, assuming that the gain of the two source followers LM1 and DM1 are the same.
Please refer to FIGS. 5A and 5B. FIG. 5A shows a schematic diagram of a conventional light node during a second sample stage (Sample 2) of a readout phase. FIG. 5B shows a schematic diagram of a conventional dark node during the second sample stage of the readout phase. As described above, Sample 2 is for sampling the reset signal, which can be represented as: (DN−LN)Sample2. According to FIGS. 5A-5B, the switches LS2 and DS2 are again closed to reset the capacitor C0 and the capacitor C1. Ideally, in the Sample 2, the voltages of the capacitors C0 and C1 should be reset to the same voltages as the power supply information V1. However, practically, the voltages of the capacitors C0 and C1 will be reset to a voltage different from V1, as shown by “V2” in FIGS. 5A and 5B. One of the reasons for this variation is the power supply noise. As a consequence, during Sample 1 of a next light node, the input of ADC is equal to (V2-Vint) multiplied by the gain of source followers, not (V1-Vint) multiplied by the gain of source followers. The result calculated by (DN−LN)Sample1−(DN−LN)Sample2 therefore varies from one light node to another light node because the voltages of the capacitors C0 and C1 are not always reset to the same power supply voltage. In a worst case, an error in the digital output generated by the ADC may be as high as 5 LSB.
To sum up, in the conventional image pixel 10, because the dark nodes 102 are one row of nodes each of which is shared by a column of light nodes 101 (as shown in FIG. 1), after the first row of light nodes are readout, all the dark nodes 102 will be reset, thereby causing the power supply information to be lost. Hence, the conventional image pixel 10 is very sensitive to power supply noise.
In view of the above, to overcome the drawback in the prior art, the present invention proposes an image pixel which is not sensitive to power supply noise and a dark node for use in the image pixel.